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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Features
* ANSI X3T11 Fibre Channel Compatible 1.0625 Gbps Full-duplex Transceiver * 10 Bit TTL Interface for Transmit and Receive Data * Monolithic Clock Synthesis and Clock Recovery - No External Components
1.0625 Gbits/sec Fibre Channel Transceiver
* 106.25 MHz TTL Reference Clock * Low Power Operation - 650 mW * Suitable for Both Coaxial and Optical Link Applications * 64 Pin, 10mm or 14mm PQFP * Single +3.3V Power Supply
General Description
The VSC7125 is a full-speed Fibre Channel Transceiver optimized for Disk Drive and other space constrained applications. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency. The VSC7125 also samples serial receive data on the RX PECL differential inputs, recovers the clock and data, deserializes it onto the 10-bit receive data bus, outputs two recovered clocks at one twentieth of the incoming baud rate and detects Fibre Channel "Comma" characters. The VSC7125 contains on-chip PLL circuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and require no external components.
VSC7125 Block Diagram
EWRAP R0:9
10
QD
Serial to Parallel / 10
Retimed Data Recovered Clock
QD Clock Recovery 2:1
RX+ RX-
RCLK RCLKN
Frame Logic / 20 Comma Detect
Resync
COM_DET EN_CDET
10
T0:9
DQ
Parallel to Serial
Serial Data Synthesized Clock
DQ
TX+ TX-
REFCLK
PLL Clock Multiply
G52121-0, Rev. 4.1
4/23/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre Channel Transceiver
Data Sheet
VSC7125
Functional Description
Clock Synthesizer
The VSC7125 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to achieve a baud rate clock at nominally 1.0625 GHz. The clock synthesizer contains a fully monolithic PLL which does not require any external components.
Serializer
The VSC7125 accepts TTL input data as a parallel 10 bit character on the T0:9 bus which is latched into the input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit T0 transmitted first. User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specification, or an equivalent, edge rich, DC-balanced code.
Transmission Character Interface
In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the VSC7125 corresponds to a transmission character. This mapping is illustrated below.
Figure 1: Transmission Order and Mapping to Fibre Channel Character
Parallel Data Bits 8B/10B Bit Position Comma Character
T9 j X
T8 h X
T7 g X
T6 f 1
T5 i 1
T4 e 1
T3 d 1
T2 c 1
T1 b 0
T0 a 0
Last Data Bit Transmitted Clock Recovery
First Data Bit Transmitted
The VSC7125 accepts differential high speed serial inputs on the RX+/RX- pins, extracts the clock and retimes the data. The serial bit stream should be encoded to provide DC balance and limited run length by a Fibre Channel compatible 8B/10B transmitter or equivalent. The VSC7125 clock recovery circuitry is completely monolithic and requires no external components. For proper operation, the baud rate of the data stream to be recovered should be within 0.01% of ten times the REFCLK frequency. For example if the REFCLK used is 106.25MHz, then the incoming serial baud rate must be 1.0625 gigabaud +0.01%.
Deserializer
The retimed serial bit stream is converted into a 10-bit parallel output character. The VSC7125 provides complementary TTL recovered clocks, RCLK and RCLKN, which are at one twentieth of the serial baud rate. This architecture is designed to simplify demultiplexing of the 10-bit data characters into a 20-bit halfword in the downstream controller chip. The clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. The serial data is retimed by the internal high-speed clock, and deserialized. The
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52121-0, Rev. 4.1
4/23/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
1.0625 Gbits/sec Fibre Channel Transceiver
resulting parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. In order to maximize the setup and hold times available at this interface, the parallel data is loaded into the output register at a point nominally midway between the transition edges of RCLK and RCLKN. If serial input data is not present, or does not meet the required baud rate, the VSC7125 will continue to produce a recovered clock so that downstream logic may continue to function. The RCLK and RCLKN output frequency under these circumstances may differ from their expected frequency by no more than +1%.
Word Alignment
The VSC7125 provides 7-bit Fibre Channel comma character recognition and data word alignment. Word synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7125 constantly examines the serial data for the presence of the Fibre Channel "comma" character. This pattern is "0011111XXX", where the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and K28.7, which is defined specifically for synchronization in Fibre Channel systems. Improper alignment of the comma character is defined as any of the following conditions: 1) The comma is not aligned within the 10-bit transmission character such that T0...T6 = "0011111" 2) The comma straddles the boundary between two 10-bit transmission characters. 3) The comma is properly aligned but occurs in the received character presented during the rising edge of RCLK rather than RCLKN. When EN_CDET is HIGH and an improperly aligned comma is encountered, the internal data is shifted in such a manner that the comma character is aligned properly in R0:9. This results in proper character and halfword alignment. When the parallel data alignment changes in response to an improperly aligned comma pattern, some data which would have been presented on the parallel output port may be lost. However, the synchronization character and subsequent data will be output correctly and properly aligned. When EN_CDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern. On encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the comma character and has a duration equal to the data, or half of an RCLK period. The COM_DET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge of RCLKN. Functional waveforms for synchronization are given in Figure 2 and Figure 3. Figure 2 shows the case when a comma character is detected and no phase adjustment is necessary. It illustrates the position of the COM_DET pulse in relation to the comma character on R0:9. Figure 3 shows the case where the K28.5 is detected, but it is out of phase and a change in the output data alignment is required. Note that up to three characters prior to the comma character may be corrupted by the realignment process.
G52121-0, Rev. 4.1
4/23/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre Channel Transceiver
Figure 2: Detection of a Properly Aligned Comma Character
Data Sheet
VSC7125
RCLK RCLKN
COM_DET
R0:9
K28.5
TChar
TChar
TChar
TChar: 10 bit Transmission Character
Figure 3: Detection and Resynchronization of an Improperly Aligned Comma
Receiving Two Consecutive K28.5+TChar Transmission Words
RCLK RCLKN
COM_DET
R0:9
Potentially Corrupted
K28.5
TChar
TChar
TChar
K28.5
TChar
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52121-0, Rev. 4.1
4/23/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Figure 4: Transmit Timing Waveforms
1.0625 Gbits/sec Fibre Channel Transceiver
REFCLK
T1
T2
T0:9 10 Bit Data
Data Valid
Data Valid
Data Valid
AC Characteristics
Table 1: Transmit AC Characteristics Parameters T1 T2 TSDR,TSDF TLAT Description T0:9 Setup time to the rising edge of REFCLK T0:9 hold time after the rising edge of REFCLK TX+/TX- rise and fall time Min
1.5
Max
--
Units
ns.
Conditions Measured between the valid data level of T0:9 to the 1.4V point of REFCLK
1.0 --
-- 300
ns. ps.
20% to 80%, 75 Ohm load to Vss, Tested on a sample basis bc = Bit clocks ns = Nano second
Trj TDJ
Latency from rising edge of 11bc - 1ns ns. REFCLK to T0 appearing on TX+/TXTransmitter Output Jitter Allocation Serial data output random -- 20 ps. jitter (RMS) Serial data output -- 100 ps. deterministic jitter (p-p)
RMS, tested on a sample basis (refer to Figure 8) Peak to peak, tested on a sample basis (refer to Figure 8)
G52121-0, Rev. 4.1
4/23/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 5
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre Channel Transceiver
Table 2: Receive AC Characteristics Parameters T1 Description Data or COM_DET Valid prior to RCLK/RCLKN rise Data or COM_DET Valid after RCLK or RCLKN rise Deviation of RCLK rising edge to RCLKN rising edge delay from nominal.
f baud delay = ------------- T 3 10
Data Sheet
VSC7125
Min.
4.0
Max.
--
Units
ns.
Conditions Measured between the 1.4V point of RCLK or RCLKN and a valid level of R0:9. All outputs driving 10pF load.
T2
3.0
--
ns.
T3
-500
500
ps.
Nominal delay is 10 bit times. Tested on sample basis
T4
Deviation of RCLK, RCLKN frequency from nominal.
f REFCLK f RCLK = ---------------------- T 4 2
-1.0
1.0
%
Whether or not locked to serial data
TR, TF Rlat TLOCK
R0:9, COM_DET, RCLK, RCLKN rise and fall time Latency from RX to R0:9 Data acquisition lock time @ 1.0625Gb/s Receive Data Jitter Power
-- 15bc + 2ns --
2.4 34bc + 2ns 2.4
ns.
Between Vil(max) and Vih(min), into 10 pf. load. bc = Bit clock ns = Nano second 8B/10B IDLE pattern. Tested on a sample basis dBc, RMS for l0-12 Bit Error Ratio Tested on a sample basis
s.
Receive Data Jitter
1 -----------------------------2 x BitTime
100KHz
-- PhaseNoise
40
ps.
Note: Probability of recovery for data acquisition is 95% per section 5.3 of the FC-PH rev. 4.3.
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52121-0, Rev. 4.1
4/23/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Figure 5: Receive Timing Waveforms
T4 T3
1.0625 Gbits/sec Fibre Channel Transceiver
RCLK RCLKN
T1 T2
Data Valid
R0:9
Data Valid
Data Valid
Figure 6: REFCLK Timing Waveforms
TL REFCLK
TH Vih(min) Vil(max)
Table 3: Reference Clock Requirements Parameters Description Min Max Unit s Conditions Range over which both transmit and receive reference clocks on any link may be centered Maximum frequency offset between transmit and receive reference clocks on one link Measured at 1.5V Between Vil(max) and Vih(min) dbc, RMS for FC compliant output data jitter
FR
Frequency Range
100
110
MHz
FO DC TRCR,TRCF REFCLK Jitter
Frequency Offset REFCLK duty cycle REFCLK rise and fall time REFCLK Jitter Power
5MHz
-200
200
ppm.
30 --
70 2.0
% ns.
100Hz
PhaseNoise
--
2
ps.
REFCLK Jitter Power REFCLK Jitter
5MHz
100Hz
PhaseNoise
--
40
ps.
dbc, RMS for 10-12 Bit Error Ratio with zero length external path. Tested on a sample basis
G52121-0, Rev. 4.1
4/23/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre Channel Transceiver
Figure 7: Parametric Measurement Information
Data Sheet
VSC7125
Serial Input Rise and Fall Time
80% 20%
TTL Input and Output Rise and Fall Time
Vih(min)
Vil(max)
Tr
Tf
Tr
Tf
Receiver Input Eye Diagram Jitter Tolerance Mask
Bit Time
Amplitude
Eye Width%
Parametric Test Load Circuit Serial Output Load TTL A.C. Output Load
Z0 = 75
75
10 pF
VDD - 2.0V
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52121-0, Rev. 4.1
4/23/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Figure 8: Transmitter Jitter Measurement Method
1.0625 Gbits/sec Fibre Channel Transceiver
BERT Pattern Generator
1.0625 GHz Clock
DATA DATA 106.25MHz Trigger
Digitizing Scope
VSC7125 TX
RJ DJ
-K28.7 -K28.7 0011111000 0011111000 -K28.5 +K28.5 0011111010 1100000101
REFCLK TX+ TXT0:9
1.0625 Gb/s Single-Ended Measurement
Random jitter (RJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section A.4.4. Measure standard deviation of all 50% crossing points. Peak to peak RJ is + 7 sigma of distribution. Deterministic jitter (DJ) measurements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section A.4.3. Measure time of all the 50% points of all ten transitions. DJ is the range of the timing variations.
Figure 9: Input Structures
VDD +3.3 V VDD +3.3 V
INPUT INPUT
Current Limit
R
INPUT
R GND GND
All Resistors 3.3K
REFCLK and TTL Inputs
High Speed Differential Input (RX+/RX-)
A
B
G52121-0, Rev. 4.1
4/23/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 9
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre Channel Transceiver
Data Sheet
VSC7125
DC Characteristics (Over recommended operating conditions).
Parameters VOH VOL
VOUT751 VOUT501 VIN1
Description Output HIGH voltage (TTL) Output LOW voltage (TTL) TX Output differential peakto-peak voltage swing TX Output differential peakto-peak voltage swing Receiver differential peak-topeak Input Sensitivity RX Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Supply voltage Power dissipation Supply Current
Min
2.4 -- 1200 1200 300 2.0 0 -- -- 3.14 -- --
Typ
-- -- -- -- -- -- -- 50 -- -- 625 190
Max
-- 0.5 2200 2200 2600 5.5 0.8 500 -500 3.47 900 260
Units
V V mVp-p mVp-p mVp-p V V A A V mW mA
Conditions IOH = -1.0 mA IOL = +1.0 mA 75 to VDD - 2.0 V (TX+ - TX-) 50 to VDD - 2.0 V (TX+ - TX-) Internally biased to Vdd/2 (RX+ - RX-) -- VIN =2.4V VIN =0.5V 3.3V5% Outputs open, VDD = VDD max Outputs open, VDD = VDD max
VIH VIL IIH IIL
VDD
PD IDD
Note: (1) Refer to Application Note, AN-37, for differential measurement techniques.
Absolute Maximum Ratings (1)
Power Supply Voltage, (VDD).............................................................................................................-0.5V to +4V DC Input Voltage (PECL inputs) ............................................................................................ -0.5V to VDD +0.5V DC Input Voltage (TTL inputs) .........................................................................................................-0.5V to 5.5V DC Output Voltage (TTL Outputs)........................................................................................ -0.5V to VDD + 0.5V Output Current (TTL Outputs) ................................................................................................................ +/-50mA Output Current (PECL Outputs)............................................................................................................... +/-50mA Case Temperature Under Bias .........................................................................................................-55o to +125oC Storage Temperature.....................................................................................................................-65oC to +150oC Maximum Input ESD (Human Body Model).............................................................................................. 1500 V
Recommended Operating Conditions
Power Supply Voltage, (VDD)................................................................................................................ +3.3V+5% Operating Temperature Range ............................................................0oC Ambient to +100oC Case Temperature
Notes: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability.
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G52121-0, Rev. 4.1
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Package Pin Descriptions
Figure 10: Pin Diagram
TX+ TXVDDP VDDD VSSANA VDDANA VSSD VDDD RX+ VDDP RXVSSD VDDD N/C
1.0625 Gbits/sec Fibre Channel Transceiver
N/C VDDP 63
VSSD T0 T1 T2 VDDD T3 T4 T5 T6 VDDD T7 T8 T9 VSSD VSSD N/C
1 3
61
59
57
55
53
51
49 47 45
5 43 7 41 9 39 11 37 13 35 15 17 19 21 23 25 27 29 31 33
N/C COMDET VSST R0 R1 R2 VDDT R3 R4 R5 R6 VDDT R7 R8 R9 VSST
(Top View)
Table 4: Pin Identification Pin #
2-4, 6-9, 11-13
Name
T0:9
INPUTS - TTL 10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of REFCLK. The data bit corresponding to T0 is transmitted first. INPUT - TTL This rising edge of this clock latches T0:9 into the input register. It also provides the reference clock, at one tenth the baud rate to the PLL. OUTPUTS - Differential PECL (AC Coupling recommended) These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. OUTPUTS - TTL 10-bit received character. Parallel data on this bus is clocked out on the rising edges of RCLK and RCLKN. R0 is the first bit received on RX+/RX-.
22
REFCLK
62, 61
TX+, TX-
45-43, 4138, 36-34
R0:9
G52121-0, Rev. 4.1
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
N/C TEST1 EWRAP TEST2 VSSD REFCLK TEST3 EN_CDET VSSD TEST4 N/C VDDD VDDT RCLKN RCLK VSST
Description
Page 11
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre Channel Transceiver
Table 4: Pin Identification Pin #
19
Data Sheet
VSC7125
Description INPUT - TTL LOW for Normal Operation. When HIGH, an internal loopback path from the transmitter to the receiver is enabled and the TX outputs are held HIGH. INPUTS - Differential PECL (AC Coupling recommended) The serial receive data inputs selected when EWRAP is LOW. Internally biased tot VDD/2, with 3.3K resistors from each input pin to VDD and GND. OUTPUT - Complementary TTL Recovered clocks derived from one twentieth of the RX+/- data stream. Each rising transition of RCLK or RCLKN corresponds to a new word on R0:9. INPUT - TTL Enables COMDET and word resynchronization when HIGH. When LOW, keeps current word alignment and disables COMDET. OUTPUT - TTL This output goes HIGH for half of an RCLK period to indicate that R0:9 contains a Comma Character (`0011111XXX'). COMDET will go HIGH only during a cycle when RCLKN is rising. COMDET is enabled by EN_CDET being HIGH. INPUT These signals are used for factory test. For normal operation, tie to VDD. OUTPUT This signal is used for factory test. For normal operation, leave open.
Analog Power Supply Analog Ground Digital Logic Power Supply
Name
EWRAP
54, 52
RX+, RX-
31, 30
RCLK, RCLKN
24
EN_CDET
47
COMDET
18,20,23
TEST1 TEST2 TEST3 TEST_4 VDDANA VSSANA VDDD
26 57 58 5, 10, 28, 50, 55, 59 1, 14, 15, 21, 25, 51, 56 29, 37, 42 32, 33, 46 53, 60, 63 16,17,27, 48,49,64
VSSD VDDT VSST VDDP N/C
Digital Logic Ground TTL Output Power Supply TTL Output Ground PECL I/O Power Supply No Connection. These pins are not internally connected.
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G52121-0, Rev. 4.1
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VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Package Information
64-pin PQFP Package Dimensions
D
1.0625 Gbits/sec Fibre Channel Transceiver
Item
D1
10 mm
2.45 2.00 13.20 10.00 13.20 10.00 0.22 0.50 0.88 0 - 7
14 mm
2.35 2.00 17.20 14.00 17.20 14.00 0.35 0.80 0.88
Tolerance
MAX +.10/-.05 .25 .10 .25 .10 .05 BASIC .15/-.10
A
64 49 48 1
A2 D D1 E E1
E1 E
b e L
16 33
17
10o TYP
32
A
A2
100 TYP
e
0.30 RAD. TYP.
A
0.20 RAD. TYP .
STANDOFF
0.25 MAX.
0.17 MAX. 0.25 L
b
0.102 MAX. LEAD COPLANARITY
NOTES: All drawings not to scale All units in mm unless otherwise noted. 10 x 10 mm Package # 101-266-1 14 x 14 mm Package # 101-262-1
G52121-0, Rev. 4.1
4/23/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
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VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre Channel Transceiver
Data Sheet
VSC7125
Package Thermal Considerations
The VSC7125 is packaged in either a 10 mm PQFP or a 14 mm PQFP with internal heat spreaders. These packages use industry-standard EIAJ footprints, but have been enhanced to improve thermal dissipation. The construction of the packages is as shown in Figure 11.
Figure 11: Package Cross Section
Aluminum Heat Spreader Plastic Molding Compound
Lead
Epoxy Bond Wire Die
Table 5: Thermal Resistance
Symbol Description Thermal resistance from junction to case Thermal resistance from case to ambient in still air including conduction through the leads. Thermal resistance from case to ambient with 100 LFM airflow Thermal resistance from case to ambient with200 LFM airflow Thermal resistance from case to ambient with 400 LFM airflow Thermal resistance from case to ambient with 600 LFM airflow 10mm Value 10.5 53 44 39 34 31 14mm Value 10 32 28 25 22 20 Units
oC/W oC/W oC/W oC/W oC/W oC/W
jc ca ca-100 ca-200 ca-400 ca-600
The VSC7125 is designed to operate with a junction temperature up to 110oC. The user must guarantee that the temperature specification is not violated. With the Thermal Resistances shown above, the 10x10mm PQFP can operate in still air ambient temperatures of 53oC [53oC=110oC-0.9W*(10.5oC/W+53oC/W)] while the 14x14 PQFP can operate in still air ambient temperatures of 73oC [73oC=110oC-0.9W*(10oC/W+32oC/W)]. If the ambient air temperature exceeds these limits then some form of cooling through a heatsink or an increase in airflow must be provided.
Moisture Sensitivity Level
This device is rated with a moisture sensitivity level 3 rating. Refer to Application Note AN-20 for appropriate handling procedures.
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G52121-0, Rev. 4.1
4/23/98
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Ordering Information
1.0625 Gbits/sec Fibre Channel Transceiver
The part number for this product is formed by a combination of the device number and the package style: VSC7125xx
Device Type:
VSC7125: 1.0625 Gbps Transceiver
Package Style (64-pin)
QN: 14x14mm PQFP QU: 10x10mm PQFP
Marking Information
The package is marked with three lines of text as shown below (QU Package):
Pin Identifier
VITESSE
VSC7125QU
#### AAAA# Package Suffix
Part Number
Date Code
Lot Tracking Code
Notice
Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. Therefore, the reader is cautioned to confirm that this datasheet is current prior to placing any orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product.
Warning
Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without written consent is prohibited.
G52121-0, Rev. 4.1
4/23/98
(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
Page 15
VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre Channel Transceiver
Data Sheet
VSC7125
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(c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896
G52121-0, Rev. 4.1
4/23/98

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